Using 8255 Programmable Peripheral Interface in ITMP Lab This is due for use in 2nd week of July 2003 Using 8255 Programmable Peripheral Interface in ITMP Lab

The 8255 Programmable Peripheral Interface chip

8255 has three 8-bit ports (PA, PB and PC) which may be used in three modes. Mode 0 is used for this labs applications. There are two 8255 available on the trainer. They are based at i/o address

8255-1 ODD address FFE1 FRC26 connector J4 on the Trainers left bottom. 8255-2 EVEN address FFE0 FRC26 connector J5 on the trainers leftjust above J4

In the view of the programmer 8255 appears as four registers

>
Address Offset Functionio address (base+offset)
FFE1/FFE0(base address) +00 Port A FFE1/FFE0
  +01 Port BFFE3/FFE2
  +02 Port CFFE5/FFE4
  +03 ControlFFE7/FFE6

In mode 0, ports A and B may be set up as 8 input lines or 8 output lines.
Port C is divided into upper and lower 4-bit sections, each of which may be set up for input or output.

FFE7/FFE6 7 6 5 4 3 2 1 0 Bit function
                0 Port C lower = output
                1 Port C lower = input
              0   Port B = output
              1   Port B = input
            0     Mode 0
            1     Mode 1
          0       Port C upper = output
          1       Port C upper = input
        0         Port A = output
        1         Port A = input
    0 0           Mode 0: Basic input/output
    0 1           Mode 1: Strobed Input/output
    1 x           Mode 2: Bi-directional Bus
  0               Mode select flag = inactive
  1               Mode select flag = active

Example: port A as output, port B as input, port C lower as output, port C upper as input control word =10001010B(8A hex)

Write the control word to control register address (odd/even) FFE7/FFE6. port A data can be Written to address FFE1/FFE0 port B data can be read from FFE3/FFE2. port C Upper data can be read from address FFE5/FFE4 (mask of Lower 4 bits of Data). port C Lower data can be Written at address FFE5/FFE4.

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